--- Log opened Mo Jun 14 19:04:22 2010 19:04 *** anthony.freenode.net changed the topic of #linux4nano-dev to: Linux4Nano *developer* discussion channel | Non-development-related messages => #linux4nano please | Unified iBugger v0.1.0, iLoader beta (2G only): http://bit.ly/oXZRO --- Log opened Mo Jun 14 20:14:46 2010 20:14 *** anthony.freenode.net changed the topic of #linux4nano-dev to: Linux4Nano *developer* discussion channel | Non-development-related messages => #linux4nano please | Unified iBugger v0.1.0, iLoader beta (2G only): http://bit.ly/oXZRO --- Log opened Mo Jun 14 20:15:16 2010 20:15 *** wolfe.freenode.net changed the topic of #linux4nano-dev to: Linux4Nano *developer* discussion channel | Non-development-related messages => #linux4nano please | Unified iBugger v0.1.0, iLoader beta (2G only): http://bit.ly/oXZRO 20:29 *** MarcelloC has joined #linux4nano-dev 20:36 *** benedikt93 has joined #linux4nano-dev 20:38 *** Marcello|PC has joined #linux4nano-dev 20:41 *** MarcelloC has quit IRC (Ping timeout: 245 seconds) 20:43 *** Marcello|PC has quit IRC (Ping timeout: 245 seconds) 20:43 < benedikt93> TheSeven: Is ARM926EJ-S ARMv5 ? 20:44 < TheSeven> ARMv5TEJ to be exact 20:44 < benedikt93> it was just because of the right version of ARM ARM 20:44 *** MarcelloC has joined #linux4nano-dev 20:45 < TheSeven> I have no clue why they are using a Jazelle processor... 20:45 < benedikt93> Maybe the games can use Java? 20:46 < TheSeven> i highly doubt that 20:46 *** Jiss has joined #linux4nano-dev 20:46 < TheSeven> it's just a very popular cellphone core, so it was probably cheap and well-tested 20:48 < benedikt93> I already asked some houres ago, what does "LDR R7, =unk_2000C580" exactly? If I interpreted this wrongly, this might be th reason why I called that code "nonsense" yesterday ;) 20:48 < TheSeven> it basically loads 0x200c580 to r7 20:48 < TheSeven> oops, missed a zero 20:49 < TheSeven> internally, that's assembled as an "LDR R7, [PC,#whatever]" instruction, which points to a data word (containing 0x2000c580) in a constant pool nearby 20:50 < benedikt93> so not the value at that adress? what is then the difference to "MOV R6, #j_reset_vector" (except the adress)? 20:50 < TheSeven> that's that the .ltorg keyword is for, in case you spot that somewhere 20:51 < TheSeven> mov r6, #whatever is a barrel shifter operand, so it can only define 8 bits, shifted by an even number of bits 20:51 < TheSeven> look at the actual encoding of those instructions to see why 20:51 < TheSeven> from a disassembling point of view, you can consider them equal 20:51 < TheSeven> the LDR Rx, =whatever macro ist just a trick to work around that limitation 20:51 < benedikt93> does it need less execution time, or why are diferrent instructions used? 20:52 < TheSeven> the LDR Rx, =... actually consists of 2 words. The actual LDR instruction, and a data word in a constant pool (a total of 8 bytes), and it is a regular memory load, which may take quite some time if it's not in the cache --- Log opened Mo Jun 14 20:53:08 2010 20:53 *** zelazny.freenode.net changed the topic of #linux4nano-dev to: Linux4Nano *developer* discussion channel | Non-development-related messages => #linux4nano please | Unified iBugger v0.1.0, iLoader beta (2G only): http://bit.ly/oXZRO 20:53 < TheSeven> the MOV variant is just a single instruction which has the data embedded into the instruction word, so you only have 4 bytes, and it's just a trivial MOV, which doesn't access memory and is thus faster 20:53 < benedikt93> and what was this .ltorg now? 20:53 < TheSeven> .ltorg tells the assembler to place a constant pool at that place 20:54 < TheSeven> the constant for the LDR macro needs to be stored within 1KB of the instruction, IIRC 20:54 < TheSeven> or maybe 4KB 20:55 < TheSeven> see the instruction encoding for an exact value 20:55 < benedikt93> so [PC,#whatever] is the position of the instrcution shifted by some offset? 20:55 < TheSeven> this limitation comes from the fact that this #whatever in the LDR will suffer from the same problem as the original MOV #whatever did 20:56 < TheSeven> LDR Rx, [PC,#whatever] => load the value at (current instruction + 8 bytes + whatever) to Rx 20:56 < TheSeven> PC will in most cases be 8 ahead of the instruction that's currently executed 20:57 < benedikt93> because of the pipelining? 20:57 < TheSeven> probably 20:59 < benedikt93> I think I now got everything I wanted to know (+ some more) ;) so thx :) 21:01 *** MarcelloC has quit IRC (Ping timeout: 245 seconds) 21:05 *** benedikt93 has quit IRC (Quit: Bye ;)) 21:08 *** MarcelloC has joined #linux4nano-dev 21:29 *** MarcelloC has quit IRC (Ping timeout: 245 seconds) 21:54 *** Jiss has quit IRC (Quit: Quitte) 23:09 *** fxb is now known as fxb__ --- Log closed Di Jun 15 00:20:11 2010